DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 469

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

 Intermittent mode 16 and intermittent mode 64
Figure 10.11 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
In intermittent mode of cycle steal, the DMAC returns the bus mastership to other bus
master whenever a unit of transfer (byte, word, longword, or 16-byte unit) is complete. If
the next transfer request occurs after that, the DMAC gets the bus mastership from other
bus master after waiting for 16 or 64 clocks in Bφ count. The DMAC then transfers data of
one unit and returns the bus mastership to other bus master. These operations are repeated
until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus
occupation by DMA transfer than cycle-steal normal mode.
This intermittent mode can be used for all transfer section; transfer request source, transfer
source, and transfer destination. The bus modes, however, must be cycle steal mode in all
channels.
Figure 10.11 Example of DMA Transfer in Cycle Steal Intermittent Mode
Bus cycle
Bus cycle
DREQ
Figure 10.10 DMA Transfer Example in Cycle-Steal Normal Mode
DREQ
CPU
CPU
(Dual Address, DREQ Low Level Detection)
(Dual Address, DREQ Low Level Detection)
CPU
CPU
CPU
CPU
DMAC DMAC CPU
Read/Write
DMAC DMAC
Read/Write
Bus mastership returned to CPU once
More than 16 or 64 Bφ
(change by the CPU's state of using bus)
Section 10 Direct Memory Access Controller (DMAC)
CPU
Rev. 3.00 May 17, 2007 Page 411 of 1582
CPU DMAC DMAC CPU
DMAC
Read/Write
Read/Write
DMAC
CPU
REJ09B0181-0300