DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 55

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 21.19
Table 21.19
Table 21.20
Table 21.20
Table 21.21
Table 21.22
Section 22 I/O Ports
Table 22.1
Table 22.2
Table 22.3
Table 22.4
Table 22.5
Table 22.6
Table 22.7
Table 22.8
Table 22.9
Table 22.10
Table 22.11
Table 22.12
Section 23 Flash Memory
Table 23.1 (1)
Table 23.1 (2)
Table 23.2
Table 23.3
Table 23.4 (1)
Table 23.4 (2)
Table 23.5
Table 23.6
Table 23.7
Table 23.8
Table 23.9
Table 23.10
Table 23.11
Table 23.12
Table 23.13
Table 23.14
Register Configuration........................................................................................ 1166
Port A Data Register (PADR) Read/Write Operations ....................................... 1172
Register Configuration........................................................................................ 1178
Port B Data Register L (PBDRL) Read/Write Operations.................................. 1180
Register Configuration........................................................................................ 1185
Port C Data Register (PCDR) Read/Write Operations........................................ 1188
Register Configuration........................................................................................ 1193
Port D Data Register (PDDR) Read/Write Operations ....................................... 1196
Register Configuration........................................................................................ 1203
Comparison of Programming Modes.................................................................. 1220
Pin Configuration................................................................................................ 1225
Register/Parameter and Target Mode ................................................................. 1227
Usable Parameters and Target Modes................................................................. 1236
Overlapping of RAM Area and User MAT Area................................................ 1251
Peripheral Clock (Pφ) Frequency that Can Automatically Adjust Bit Rate
of This LSI.......................................................................................................... 1253
Hardware Protection ........................................................................................... 1271
SH7085 Pin Functions in Each Operating Mode (1)....................................... 1016
SH7085 Pin Functions in Each Operating Mode (2)....................................... 1021
SH7086 Pin Functions in Each Operating Mode (1)....................................... 1026
SH7086 Pin Functions in Each Operating Mode (2)....................................... 1032
Register Configuration.................................................................................... 1038
Transmit Forms of Input Functions Allocated to Multiple Pins ..................... 1160
Port E Data Register (PEDR) Read/Write Operations .................................... 1207
Register Configuration.................................................................................... 1212
Port F Data Register L (PFDRL) Read/Write Operations............................... 1214
Software Protection......................................................................................... 1272
Initiation Intervals of User Branch Processing ............................................... 1281
Initial User Branch Processing Time .............................................................. 1281
Inquiry and Selection Commands ................................................................... 1287
Programming and Erasure Commands............................................................ 1301
Relationship between FWE and MD Pins and Operating Modes
(SH7083 and SH7084) ................................................................................... 1219
Relationship between FWE and MD Pins and Operating Modes
(SH7085 and SH7086) ................................................................................... 1219
Register Configuration................................................................................... 1226
Parameter Configuration ................................................................................ 1226
Rev. 3.00 May 17, 2007 Page lv of Iviii