DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 88

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 2 CPU
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly in memory.
Delayed Branching: Unconditional branch instructions means the delayed branch instructions.
With a delayed branch instruction, the branch is made after execution of the instruction
immediately following the delayed branch instruction. This minimizes disruption of the pipeline
when a branch is made. The conditional branch instructions have two types of instructions:
conditional branch instructions and delayed branch instructions.
Table 2.3
Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is
executed in one to two cycles, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in two
to three cycles. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and-
accumulate operation are each executed in two to four cycles.
T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is
performed according to whether the result is True or False. Processing speed has been improved
by keeping the number of instructions that modify the T bit to a minimum.
Table 2.4
Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword
immediate data is not placed in the instruction code. It is placed in a table in memory. The table in
memory is accessed with the MOV immediate data instruction using PC relative addressing mode
with displacement.
Rev. 3.00 May 17, 2007 Page 30 of 1582
REJ09B0181-0300
CPU in this LSI
BRA
ADD
CPU in this LSI
CMP/GE
BT
BF
ADD
CMP/EQ
BT
TRGET
R1,R0
R1,R0
TRGET0
TRGET1
#−1,R0
#0,R0
TRGET
Delayed Branch Instructions
T Bit
Description
ADD is executed before branch to TRGET.
Description
When R0 ≥ R1, the T bit is set.
When R0 ≥ R1, a branch is made to TRGET0. BGE
When R0 < R1, a branch is made to TRGET1. BLT
The T bit is not changed by ADD.
When R0 = 0, the T bit is set.
A branch is made when R0 = 0.
Example of Other CPUs
ADD.W R1,R0
BRA
Example of Other CPUs
CMP.W R1,R0
SUB.W #1,R0
BEQ
TRGET0
TRGET1
TRGET
TRGET