LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 278

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
13.8.2 OTG Interrupt Status Register (OTGIntSt - 0x5000 C100)
13.8.3 OTG Interrupt Enable Register (OTGIntEn - 0x5000 C104)
13.8.4 OTG Interrupt Set Register (OTGIntSet - 0x5000 C20C)
Table 257. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description
Bits in this register are set by hardware when the interrupt event occurs during the HNP
handoff sequence. See
Table 258. OTG Interrupt Status register (OTGIntSt - address 0x5000 C100) bit description
Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate
an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT
interrupt line in the USBIntSt register.
The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.
Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register.
Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.
Bit
4
5
6
7
8
30:9
31
Bit
0
1
2
3
31:4
Symbol
USB_ATX_INT
USB_OTG_INT
USB_I2C_INT
-
USB_NEED_CLK
-
EN_USB_INTS
Symbol
TMR
REMOVE_PU
HNP_FAILURE
HNP_SUCCESS
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 13.9
Description
External ATX interrupt line status. This bit is read-only.
OTG interrupt line status. This bit is read-only.
I
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
USB need clock indicator. This bit is read-only.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Enable all USB interrupts. When this bit is cleared, the
NVIC does not see the ORed output of the USB interrupt
lines.
Description
Timer time-out.
Remove pull-up.
This bit is set by hardware to indicate that software
needs to disable the D+ pull-up resistor.
HNP failed.
This bit is set by hardware to indicate that the HNP
switching has failed.
HNP succeeded.
This bit is set by hardware to indicate that the HNP
switching has succeeded.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
2
C module interrupt line status. This bit is read-only.
for more information on when these bits are set.
Chapter 13: LPC17xx USB OTG
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
0
0
0
NA
1
NA
1
Reset
Value
0
0
0
0
NA