LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 352

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 317. CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description
[1]
[2]
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
31:8
During a Hardware reset or when the Bus Status bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit
is set '0' the CAN Controller will wait for:
- one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by a Hardware reset or a CPU-initiated
reset.
- 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the
Bus-On mode.
This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode can
be used e.g. for software driven bit rate detection and "hot plugging".
Symbol Value
RM
LOM
[6]
STM
TPM
SM
RPM
-
TM
-
[1][6]
[5]
[3][6]
[4]
[3][2]
0 (normal)
1 (reset)
0 (normal)
1 (listen only)
0 (normal)
1 (self test)
0 (CAN ID)
1 (local prio)
0 (wake-up)
1 (sleep)
0 (low active)
1 (high active)
-
0 (disabled)
1 (enabled)
Function
Reset Mode.
The CAN Controller is in the Operating Mode, and certain registers can not
be written.
CAN operation is disabled, writable registers can be written and the current
transmission/reception of a message is aborted.
Listen Only Mode.
The CAN controller acknowledges a successfully received message on the
CAN bus. The error counters are stopped at the current value.
The controller gives no acknowledgment, even if a message is successfully
received. Messages cannot be sent, and the controller operates in “error
passive” mode. This mode is intended for software bit rate detection and
“hot plugging”.
Self Test Mode.
A transmitted message must be acknowledged to be considered successful.
The controller will consider a Tx message successful even if there is no
acknowledgment received.
In this mode a full node test is possible without any other active node on the
bus using the SRR bit in CANxCMR.
Transmit Priority Mode.
The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.
The transmit priority for 3 Transmit Buffers depends on the contents of the
Tx Priority register within the Transmit Buffer.
Sleep Mode.
Normal operation.
The CAN controller enters Sleep Mode if no CAN interrupt is pending and
there is no bus activity. See the Sleep Mode description
page
Receive Polarity Mode.
RD input is active Low (dominant bit = 0).
RD input is active High (dominant bit = 1) -- reverse polarity.
Reserved, user software should not write ones to reserved bits.
Test Mode.
Normal operation.
The TD pin will reflect the bit, detected on RD pin, with the next positive
edge of the system clock.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
371.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
Section 16.8.2 on
UM10360
© NXP B.V. 2010. All rights reserved.
Reset
Value
1
0
0
0
0
0
0
0
NA
352 of 840
RM
Set
1
x
x
x
0
x
0
x