LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 597

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 551. DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018)
Table 552. DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C)
Table 553. DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)
UM10360
User manual
Bit
7:0
31:8
Bit
7:0
31:8
Bit
15:0
31:16
Name
RawIntErrStat
-
Name
EnabledChannels
-
Name
SoftBReq
-
31.5.8 DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C)
31.5.9 DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)
The DMACEnbldChns Register is read-only and indicates which DMA channels are
enabled, as indicated by the Enable bit in the DMACCxConfig Register. A 1 bit indicates
that a DMA channel is enabled. A bit is cleared on completion of the DMA transfer.
Table 552
The DMACSoftBReq Register is read/write and enables DMA burst requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Reading the register indicates which sources are requesting DMA burst
transfers. A request can be generated from either a peripheral or the software request
register. Each bit is cleared when the related transaction has completed.
the bit assignments of the DMACSoftBReq Register.
Note: It is recommended that software and hardware peripheral requests are not used at
the same time.
shows the bit assignments of the DMACEnbldChns Register.
Function
Status of the error interrupt for DMA channels prior to masking. Each bit represents
one channel:
0 - the corresponding channel has no active error interrupt request.
1 - the corresponding channel does have an active error interrupt request.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Enable status for DMA channels. Each bit represents one channel:
0 - DMA channel is disabled.
1 - DMA channel is enabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Software burst request flags for each of 16 possible sources. Each bit represents one
DMA request line or peripheral function (refer to
connections to the DMA controller):
0 - writing 0 has no effect.
1 - writing 1 generates a DMA burst request for the corresponding request line.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Table 543
for peripheral hardware
UM10360
© NXP B.V. 2010. All rights reserved.
Table 553
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