LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 532

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description
Table 470. MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060) bit description
Table 471. MCPWM Count Control clear address (MCCAPCON_CLR - 0x400B 8064) bit description
UM10360
User manual
Bit
13
14
15
16
17
28:18 -
29
30
31
Bit
31:0
Bit
31:0
Symbol
TC2MCI0_FE
TC2MCI1_RE
TC2MCI1_FE
TC2MCI2_RE
TC2MCI2_FE
CNTR0
CNTR1
CNTR2
Description
Writing one(s) to this write-only address sets the corresponding bit(s) in the MCCNTCON register. See
Description
Writing one(s) to this write-only address clears the corresponding bit(s) in the MCCNTCON register. See
Table
25.7.4.2 MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060)
25.7.4.3 MCPWM Count Control clear address (MCCNTCON_CLR - 0x400B 8064)
25.7.5 MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018,
469.
Writing one(s) to this write-only address sets the corresponding bit(s) in MCCNTCON.
Writing one(s) to this write-only address clears the corresponding bit(s) in MCCNTCON.
0x400B 801C, 0x400B 8020)
These registers hold the current values of the 32-bit counter/timers for channels 0-2. Each
value is incremented on every PCLK, or by edges on the MCI0-2 pins, as selected by
MCCNTCON. The timer/counter counts up from 0 until it reaches the value in its
corresponding MCPER register (or is stopped by writing to MCCON_CLR).
A TC register can be read at any time. In order to write to the TC register, its channel must
be stopped. If not, the write will not take place, no exception is generated.
Value Description
1
0
1
0
1
0
1
0
1
0
-
1
0
1
0
1
0
If MODE2 is 1, counter 2 advances on a falling edge on MCI0.
A falling edge on MCI0 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a rising edge on MCI1.
A rising edge on MCI1 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a falling edge on MCI1.
A falling edge on MCI1 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a rising edge on MCI2.
A rising edge on MCI2 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a falling edge on MCI2.
A falling edge on MCI2 does not affect counter 2.
Reserved.
Channel 0 is in counter mode.
Channel 0 is in timer mode.
Channel 1 is in counter mode.
Channel 1 is in timer mode.
Channel 2 is in counter mode.
Channel 2 is in timer mode.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 25: LPC17xx Motor control PWM
UM10360
© NXP B.V. 2010. All rights reserved.
Table
532 of 840
0
0
0
0
0
0
0
0
Reset
Value
-
469.