LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 362

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 322. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit
UM10360
User manual
Bit
23
31:24 -
Symbol Value Function
SAM
description
16.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018,
0
1
Baud rate prescaler
The period of the CAN system clock t
bit timing. The CAN system clock t
Synchronization jump width
To compensate for phase shifts between clock oscillators of different bus controllers, any
bus controller must re-synchronize on any relevant signal edge of the current
transmission. The synchronization jump width t
cycles a certain bit period may be shortened or lengthened by one re-synchronization:
Time segment 1 and time segment 2
Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit period
and the location of the sample point:
CAN2EWL - 0x4004 8018)
This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read
at any time but can only be written if the RM bit in CANmod is 1.
Sampling
The bus is sampled once (recommended for high speed buses)
The bus is sampled 3 times (recommended for low to medium speed buses to filter
spikes on the bus-line)
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
t
t
TSEG1
TSEG2
t
SCL
t
SCL
SJW
t
SCL
SYNCSEG
=
=
=
is calculated using the following equation:
=
t
t
t
CANsuppliedCLK
SCL
SCL
is programmable and determines the individual
t
SCL
×
×
×
=
(
(
SJW
TSEG1
TSEG2
(
t
SJW
SCL
defines the maximum number of clock
+
+
+
×
1
1
1
(
)
BRP
Chapter 16: LPC17xx CAN1/2
)
)
+
1
)
UM10360
© NXP B.V. 2010. All rights reserved.
Reset
Value
0
NA
362 of 840
RM
Set
X
(5)
(6)
(7)
(8)
(9)