LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 364

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 324. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description
[1]
[2]
UM10360
User manual
Bit
10
11
12
13
14
15
16
17
18
19
20
21
22
23
31:24 -
If the CPU tries to write to this Transmit Buffer when the Transmit Buffer Status bit is '0' (locked), the written byte is not accepted and is
lost without this being signalled.
The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit
is set '1' for this TX buffer. The Transmission Complete Status bit remains '0' until a message is transmitted successfully.
Symbol Value
TBS2
TCS2
RS
TS2
ES
BS
RBS
DOS
TBS3
TCS3
RS
TS3
ES
BS
[1]
[1]
[2]
[2]
0(locked)
1(released)
0(incomplete) The previously requested transmission for Tx Buffer 2 is not complete.
1(complete)
0(idle)
1(transmit)
0(locked)
1(released)
0(incomplete) The previously requested transmission for Tx Buffer 3 is not complete.
1(complete)
0(idle)
1(transmit)
Function
Transmit Buffer Status 2.
Software cannot access the Tx Buffer 2 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
Software may write a message into the Transmit Buffer 2 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
Transmission Complete Status.
The previously requested transmission for Tx Buffer 2 has been successfully
completed.
Receive Status. This bit is identical to the RS bit in the GSR.
Transmit Status 2.
There is no transmission from Tx Buffer 2.
The CAN Controller is transmitting a message from Tx Buffer 2.
Error Status. This bit is identical to the ES bit in the CANxGSR.
Bus Status. This bit is identical to the BS bit in the CANxGSR.
Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
Transmit Buffer Status 3.
Software cannot access the Tx Buffer 3 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
Software may write a message into the Transmit Buffer 3 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
Transmission Complete Status.
The previously requested transmission for Tx Buffer 3 has been successfully
completed.
Receive Status. This bit is identical to the RS bit in the GSR.
Transmit Status 3.
There is no transmission from Tx Buffer 3.
The CAN Controller is transmitting a message from Tx Buffer 3.
Error Status. This bit is identical to the ES bit in the CANxGSR.
Bus Status. This bit is identical to the BS bit in the CANxGSR.
Reserved, the value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
0
Reset
Value
1
1
1
1
0
0
0
1
1
1
1
0
0
NA
364 of 840
RM
Set
1
x
0
0
0
0
0
0
1
x
0
0
0
0