LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 754

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 642.
UM10360
User manual
Handler
Hard fault
Memory
management
fault
Bus fault
Usage fault
Fault status and fault address registers
34.3.4.2 Fault escalation and hard faults
34.3.4.3 Fault status registers and fault address registers
Status register
name
HFSR
MMFSR
BFSR
UFSR
All faults exceptions except for hard fault have configurable exception priority, see
Section 34.4.3.9 “System Handler Priority
the handlers for these faults, see
Register”.
Usually, the exception priority, together with the values of the exception mask registers,
determines whether the processor enters the fault handler, and whether a fault handler
can preempt another fault handler. as described in
In some situations, a fault with configurable priority is treated as a hard fault. This is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to
hard fault occurs when:
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault
does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the
fault handler executes even though the stack push for the handler failed. The fault handler
operates but the stack contents are corrupted.
Remark: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can
preempt any exception other than Reset, NMI, or another hard fault.
The fault status registers indicate the cause of a fault. For bus faults and memory
management faults, the fault address register indicates the address accessed by the
operation that caused the fault, as shown in
•
•
•
•
A fault handler causes the same kind of fault as the one it is servicing. This escalation
to hard fault occurs because a fault handler cannot preempt itself because it must
have the same priority as the current priority level.
A fault handler causes a fault with the same or lower priority as the fault it is servicing.
This is because the handler for the new fault cannot preempt the currently executing
fault handler.
An exception handler causes a fault for which the priority is the same as or lower than
the currently executing exception.
A fault occurs and the handler for that fault is not enabled.
Address register
name
-
MMFAR
-
BFAR
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Register description
Section 34.4.3.12 “Hard Fault Status Register”
Section 34.4.3.13 “Memory Management Fault Address Register”
Section 34.4.3.11.1 “Memory Management Fault Status Register”
Section 34.4.3.11.2 “Bus Fault Status Register”
Section 34.4.3.14 “Bus Fault Address Register”
Section 34.4.3.11.3 “Usage Fault Status Register”
Section 34.4.3.10 “System Handler Control and State
Chapter 34: Appendix: Cortex-M3 user guide
Registers”. Software can disable execution of
Table
642.
Section
34.3.3.
UM10360
© NXP B.V. 2010. All rights reserved.
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