LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 797

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
34.5 ARM Cortex-M3 User Guide: Glossary
UM10360
User manual
Abort — A mechanism that indicates to a processor that the value associated with a
memory access is invalid. An abort can be caused by the external or internal memory
system as a result of attempting to access invalid instruction or data memory.
Aligned — A data item stored at an address that is divisible by the number of bytes that
defines the data size is said to be aligned. Aligned words and halfwords have addresses
that are divisible by four and two respectively. The terms word-aligned and
halfword-aligned therefore stipulate addresses that are divisible by four and two
respectively.
Banked register — A register that has multiple physical copies, where the state of the
processor determines which copy is used. The Stack Pointer, SP (R13) is a banked
register.
Base register — In instruction descriptions, a register specified by a load or store
instruction that is used to hold the base value for the instruction’s address calculation.
Depending on the instruction and its addressing mode, an offset can be added to or
subtracted from the base register value to form the address that is sent to memory. See
also Index register.
Big-endian (BE) — Byte ordering scheme in which bytes of decreasing significance in a
data word are stored at increasing addresses in memory. See also Byte-invariant,
Endianness, Little-endian.
Big-endian memory — Memory in which:
See also Little-endian memory.
Breakpoint — A breakpoint is a mechanism provided by debuggers to identify an
instruction at which program execution is to be halted. Breakpoints are inserted by the
programmer to enable inspection of register contents, memory locations, variable values
at fixed points in the program execution to test that the program is operating correctly.
Breakpoints are removed after the program is successfully tested.
Byte-invariant — In a byte-invariant system, the address of each byte of memory
remains unchanged when switching between little-endian and big-endian operation.
When a data item larger than a byte is loaded from or stored to memory, the bytes making
up that data item are arranged into the correct order depending on the endianness of the
memory access.
An ARM byte-invariant implementation also supports unaligned halfword and word
memory accesses. It expects multi-word accesses to be word-aligned.
Cache — A block of on-chip or off-chip fast access memory locations, situated between
the processor and main memory, used for storing and retrieving copies of often used
instructions, data, or instructions and data. This is done to greatly increase the average
speed of memory accesses and so improve processor performance.
•
•
a byte or halfword at a word-aligned address is the most significant byte or halfword
within the word at that address
a byte at a halfword-aligned address is the most significant byte within the halfword at
that address.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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