LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 773
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1759FBD80,551
Manufacturer:
LT
Quantity:
375
Company:
Part Number:
LPC1759FBD80,551
Manufacturer:
NXP Semiconductors
Quantity:
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Part Number:
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Manufacturer:
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NXP Semiconductors
UM10360
User manual
34.4.3.8 Configuration and Control Register
Table 661. SCR bit assignments
The CCR controls entry to Thread mode and enables:
See the register summary in
The bit assignments are shown in
Bits
[31:5]
[4]
[3]
[2]
[1]
[0]
•
•
•
the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore bus
faults
trapping of divide by zero and unaligned accesses
access to the STIR by unprivileged software, see
Name
-
SEVONPEND
-
SLEEPDEEP
SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
Reserved.
Send Event on Pending bit:
0 = only enabled interrupts or events can wakeup the processor,
disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts,
can wakeup the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting
for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or
an external event.
Reserved.
Controls whether the processor uses sleep or deep sleep as its low
power mode:
0 = sleep
1 = deep sleep.
Thread mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
Reserved.
Table 654
Table
for the CCR attributes.
662.
Chapter 34: Appendix: Cortex-M3 user guide
Table
652.
UM10360
© NXP B.V. 2010. All rights reserved.
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