LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 455

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Fig 95. Format and states in the Slave Receiver mode
reception of the own
Slave address and one
or more Data bytes all
are acknowledged
last data byte
received is Not
acknowledged
arbitration lost as
Master and addressed
as Slave
reception of the
General Call address
and one or more Data
bytes
last data byte is Not
acknowledged
arbitration lost as
Master and addressed
as Slave by General
Call
DATA
n
A
S
from Master to Slave
from Slave to Master
any number of data bytes and their associated Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of the I
bus
All information provided in this document is subject to legal disclaimers.
GENERAL CALL
SLA
Rev. 2 — 19 August 2010
W
60H
68H
70h
78h
A
A
A
A
DATA
DATA
80H
90h
A
A
DATA
DATA
Chapter 19: LPC17xx I2C0/1/2
2
C
80H
88H
90h
98h
A
A
A
A
UM10360
P OR S
P OR S
P OR S
P OR S
© NXP B.V. 2010. All rights reserved.
A0H
A0H
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