LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 790

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.4.5.4.1 The ADDR field
34.4.5.5 MPU Region Attribute and Size Register
Table 684. RBAR bit assignments
The ADDR field is bits[31:N] of the RBAR. The region size, as specified by the SIZE field
in the RASR, defines the value of N:
If the region size is configured to 4GB, in the RASR, there is no valid ADDR field. In this
case, the region occupies the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64KB region must
be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.
The RASR defines the region size and memory attributes of the MPU region specified by
the RNR, and enables that region and any subregions. See the register summary in
Table 680
RASR is accessible using word or halfword accesses:
The bit assignments are shown in
[31:N]
[(N-1):5]
[4]
[3:0]
•
•
N = Log
the most significant halfword holds the region attributes
the least significant halfword holds the region size and the region and subregion
enable bits.
ADDR
-
VALID
REGION MPU region field:
2
for its attributes.
(Region size in bytes),
All information provided in this document is subject to legal disclaimers.
Region base address field. The value of N depends on the region size. For
more information see
Reserved.
MPU Region Number valid bit:
Write:
0 = RNR not changed, and the processor:
1 = the processor:
Always reads as zero.
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the RNR.
•
•
•
•
Rev. 2 — 19 August 2010
updates the base address for the region specified in the RNR
ignores the value of the REGION field
updates the value of the RNR to the value of the REGION field
updates the base address for the region specified in the REGION field.
Table
Section
685.
Chapter 34: Appendix: Cortex-M3 user guide
34.4.5.4.1.
UM10360
© NXP B.V. 2010. All rights reserved.
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