Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 109

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

PS022517-0508
External Driver Enable
multi-node network. The following MULTIPROCESSOR modes are available in hard-
ware:
•
•
•
These modes are selected with
MULTIPROCESSOR modes, bit
The first scheme is enabled by writing
address bytes cause an interrupt, while data bytes never cause an interrupt. The ISR
must manually check the address byte that caused triggered the interrupt. If it
matches the UART address, the software should clear MPMD[0]. At this point, each new
incoming byte interrupts the CPU. The software is then responsible for determining the
end-of-frame. It checks for the end-of-frame by reading the
Status 1 Register for each incoming byte. If
address of this new frame is different from the UART’s address, then
to 1 causing the UART interrupts to go inactive until the next address byte. If the new
frame’s address matches the UART’s address, then the data in the new frame should be
processed as well.
The second scheme is enabled by setting MPMD[1:0] to
address into the UART Address Compare Register. This mode introduces more hardware
control, interrupting only on frames that match the UART’s address. When an incoming
address byte does not match the UART’s address, it is ignored. All successive data bytes in
this frame are also ignored. When a matching address byte occurs, an interrupt is issued
and further interrupts occur on each successive data byte. The first data byte in the frame
contains the NEWFRM=1 in the UART Status 1 Register. When the next address byte
occurs, the hardware compares it to the UART’s address. If there is a match, the interrupts
continue and the NEWFRM bit is set for the first byte of the new frame. If there is no match,
then the UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame is still accompanied by a NEWFRM assertion.
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and STOP bits as displayed in
signal asserts when a byte is written to the UART Transmit Data Register. The Driver
Interrupt on all address bytes.
Interrupt on matched address bytes and correctly framed data bytes.
Interrupt only on correctly framed data bytes.
MPMD[1:0]
MPEN
01b
of the UART Control 1 Register must be set to 1.
to
in the UART Control 1 Register. For all
MPRX=1
MPMD[1:0]
Figure15
Universal Asynchronous Receiver/Transmitter
, then a new frame begins. If the
Z8 Encore! XP
on page 97. The Driver Enable
10b
. In this mode, all incoming
MPRX
and writing the UART’s
Product Specification
bit of the UART
MPMD[0]
®
F0822 Series
must be set
96