Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 124

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

PS022517-0508
Baud Rate
IR_RXD
UART’s
Clock
RXD
Caution:
Receiving IrDA Data
8-clock
delay
Start Bit = 0
Data received from the infrared transceiver through the IR_RXD signal through the RXD
pin is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate
clock is used by the Infrared Endec to generate the demodulated signal (RXD) that drives
the UART. Each UART/Infrared data bit is 16-clocks wide.
tion. When the Infrared Endec is enabled, the UART’s RXD signal is internal to the Z8
Encore! XP
RXD pin.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (or in other words 24 baud clock
periods since the previous pulse was detected). This gives the Endec a sampling window
16-clock
min. 1.6
period
The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.6
pulse
Start Bit = 0
μ
s minimum width pulses allowed by the IrDA standard.
μ
16-clock
s
period
®
F0822 Series products while the IR_RXD signal is received through the
Data Bit 0 = 1
Data Bit 0 = 1
Figure 19. Infrared Data Reception
16-clock
period
Data Bit 1 = 0
Data Bit 1 = 0
16-clock
period
Data Bit 2 = 1
Z8 Encore! XP
Data Bit 2 = 1
Figure 19
16-clock
period
Product Specification
Infrared Encoder/Decoder
Data Bit 3 = 1
displays data recep-
®
F0822 Series
Data Bit 3 = 1
111