Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 73

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

PS022517-0508
Interrupt Vectors and Priority
Interrupt Assertion
Software Interrupt Assertion
Caution:
Caution:
Note:
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all the
interrupts were enabled with identical interrupt priority (all as Level 2 interrupts), then
interrupt priority would be assigned from highest to lowest as specified in
Level 3 interrupts always have higher priority than Level 2 interrupts which in turn always
have higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1,
Level 2, or Level 3), priority is assigned as specified in
enabled), and Illegal Instruction Trap always have highest priority.
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corre-
sponding bit in the Interrupt Request Register is cleared until the next interrupt occurs.
Writing a 0 to the corresponding bit in the Interrupt Request Register likewise clears
the interrupt request.
Program code generates interrupts directly. Writing 1 to the desired bit in the Interrupt
Request Register triggers an interrupt (assuming that interrupt is enabled). When the
interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request Regis-
ter is automatically cleared to 0.
Good coding style that avoids lost interrupt requests:
The following style of coding to clear bits in the Interrupt Request Registers
is not recommended. All incoming interrupts received between execution of
the first LDX command and the last LDX command is lost.
Poor coding style resulting in lost interrupt requests:
To avoid missing interrupts, the following style of coding to clear bits in the
Interrupt Request 0 register is recommended:
The following style of coding to generate software interrupts by setting bits
in the Interrupt Request Registers is not recommended. All incoming
interrupts received between execution of the first LDX command and the last
LDX command is lost.
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
ANDX IRQ0, MASK
Table
Z8 Encore! XP
24. Reset, WDT interrupt (if
Product Specification
®
Interrupt Controller
Table
F0822 Series
24.
60