Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 154

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

Table 72. I
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
I
2
C Control Register
2
C Control Register (I2CCTL)
R/W
IEN
7
RD—Read
This bit indicates the direction of transfer of the data. It is active High during a read. The
status of this bit is determined by the least-significant bit of the I
START bit is set.
TAS—Transmit Address State
This bit is active High while the address is being shifted out of the I
DSS—Data Shift State
This bit is active High while data is being shifted to or from the I
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START
cleared by setting the
perform a
The I
IEN—I
1 = The I
0 = The I
START—Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I
sends the START condition or if the IEN bit is deasserted. If this bit is 1, it cannot be
cleared to 0 by writing to the register. After this bit is set, the Start condition is sent if
there is data in the I
ters, the I
the I
and the acknowledge phase completes. If the STOP bit is also set, it also waits until the
STOP condition is sent before sending the START condition.
STOP—Send Stop Condition
This bit causes the I
register has completed transmission or after a byte is received in a receive operation. Once
2
2
C Controller is shifting out data, it generates a START condition after the byte shifts
C Control Register
nor the
2
START
C Enable
R/W1
2
2
2
C transmitter and receiver are enabled.
C transmitter and receiver are disabled.
STOP
C Controller waits until the data register is written. If this bit is set while
6
STOP
or a repeated
2
2
C Data or I
C Controller to issue a STOP condition after the byte in the I
bit is active. When set, this bit generates an interrupt that can only be
STOP
R/W1
START
5
(Table
or
START
2
STOP
72) enables the I
C Shift register. If there is no data in one of these regis-
BIRQ
R/W
4
.
bit, allowing you to specify whether you want to
F52H
0
R/W
TXI
3
2
C operation.
Z8 Encore! XP
R/W1
NAK
2
Product Specification
2
2
C Shift register after the
C Shift Register.
2
FLUSH
C Shift Register.
2
C Controller after it
W1
1
®
F0822 Series
I2C Controller
FILTEN
2
R/W
C Shift
0
141