Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 147

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

PS022517-0508
Write Transaction with a 10-Bit Address
9. Software responds by writing the second byte of address into the contents of the I
10. The I
11. If the I
12. The I
13. The I
14. Software responds by setting the STOP bit in the I
15. Software polls the STOP bit of the I
16. Software checks the ACK bit of the I
Figure 29
indicate data transferred from the I
data transferred from the slaves to the I
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 7-
bit addressing.
S
Slave Address
Figure 29. 10-Bit Addressed Slave Data Transfer Format
Data Register.
signal.
high period of SCL the I
Continue with
If the slave does not acknowledge the first address byte, the I
NCKI bit and clears the ACK bit in the I
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
Register (2nd byte of address).
bit has been sent, the Transmit Interrupt is asserted.
can be cleared at the same time.
STOP bit when the transaction is completed (STOP condition has been sent).
ACK bit is equal to 1. If the slave does not acknowledge, the ACK bit is equal
to 0. The NCKI interrupt do not occur because the STOP bit was set.
1st 7 bits
2
2
2
displays the data transfer format for a 10-bit addressed slave. Shaded regions
C Controller shifts the rest of the first byte of address and write bit out the SDA
C Controller loads the I
C Controller shifts the second address byte out the SDA signal. After the first
2
C Slave sends an acknowledge by pulling the SDA signal low during the next
step
W = 0 A
12.
2
C Controller sets the ACK bit in the I
2
2
C Shift register with the contents of the I
C Controller to slaves and unshaded regions indicate
Slave Address
2
2
C Controller.
C Control Register. Hardware deasserts the
2
2nd Byte
C Status register. If the slave acknowledged, the
2
C Status register. Software response to the
11110XX
2
C Control Register. The TXI bit
Z8 Encore! XP
. The two bits
A Data A Data A/A P/S
Product Specification
2
C Controller sets the
2
C Status register.
®
F0822 Series
XX
2
C Data
I2C Controller
are the two
2
C
134