Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 80

IC ENCORE XP MCU FLASH 4K 20SSOP

Z8F042AHH020EG

Manufacturer Part Number
Z8F042AHH020EG
Description
IC ENCORE XP MCU FLASH 4K 20SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet

Specifications of Z8F042AHH020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4156
Z8F042AHH020EG
Table 37. Interrupt Edge Select Register (IRQES)
Table 38. Interrupt Control Register (IRQCTL)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
Interrupt Edge Select Register
Interrupt Control Register
7
7
IRQE
IES7
R/W
The Interrupt Edge Select (IRQES) register
generated for the rising edge or falling edge on the selected GPIO Port input pin. The
minimum pulse width must be greater than 1 system clock to guarantee capture of the edge
triggered interrupt. Edge detection for pulses less than 1 system clock are not guaranteed.
IESx—Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input.
1 = An interrupt request is generated on the rising edge of the PAx input.
Where x indicates the specific GPIO Port pin number (0 through 7).
The Interrupt Control (IRQCTL) register
interrupts.
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a
DI
register write of a 0 to this bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0
instruction, eZ8 CPU acknowledgement of an interrupt request, Reset or by a direct
6
6
IES6
5
5
IES5
4
4
IES4
FCDH
FCFH
R/W
0
(Table
0
3
3
Reserved
(Table
IES3
R
38) contains the master enable bit for all
37) determines whether an interrupt is
2
2
Z8 Encore! XP
IES2
Product Specification
1
1
IES1
®
Interrupt Controller
F0822 Series
0
0
IES0
67

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