Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 56

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

Stop Mode Recovery
Table 10. Stop Mode Recovery Sources and Resulting Action
PS022517-0508
Operating Mode Stop Mode Recovery Source
STOP mode
External Pin Reset
On-Chip Debugger Initiated Reset
The RESET pin contains a Schmitt-triggered input, an internal pull-up, an analog filter,
and a digital filter to reject noise. After the RESET pin is asserted for at least 4 system
clock cycles, the device progresses through the System Reset sequence. While the RESET
input pin is asserted Low, Z8 Encore! XP F0822 Series device continues to be held in the
Reset state. If the RESET pin is held Low beyond the System Reset time-out, the device
exits the Reset state immediately following RESET pin deassertion. Following a System
Reset initiated by the external RESET pin, the EXT status bit in the Watchdog Timer Con-
trol Register (WDTCTL) is set to 1.
A POR is initiated using the OCD by setting the
OCD block is not reset but the rest of the chip goes through a normal system reset. The
RST
bit in the WDT Control Register is set.
STOP mode is entered by execution of a
information on STOP mode, see
Recovery, the device is held in reset for 66 cycles of the WDT oscillator followed by 16
cycles of the system clock. Stop Mode Recovery only affects the contents of the WDT
Control Register and does not affect any other values in the Register File,
including the Stack Pointer, Register Pointer, Flags, Peripheral Control Registers, and
General-Purpose RAM.
The eZ8 CPU fetches the Reset vector at Program Memory addresses
and loads that value into the Program Counter. Program execution begins at the Reset
vector address. Following Stop Mode Recovery, the STOP bit in the WDT Control
Register is set to 1.
The text following provides more detailed information on each of the Stop Mode Recov-
ery sources.
WDT time-out when configured for Reset Stop Mode Recovery
WDT time-out when configured for
interrupt
Data transition on any GPIO Port pin
enabled as a Stop Mode Recovery source
bit automatically clears during the system reset. Following the system reset, the
Table 10
lists the Stop Mode Recovery sources and resulting actions.
Low-Power Modes
STOP
instruction by the eZ8 CPU. For detailed
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Stop Mode Recovery
Action
RST
on page 45. During Stop Mode
bit in the OCD Control Register. The
Z8 Encore! XP
Reset and Stop Mode Recovery
Product Specification
0002H
®
F0822 Series
and
0003H
POR
43