Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 53

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

Reset Sources
Table 9. Reset Sources and Resulting Reset Type
PS022517-0508
Operating Mode
NORMAL or HALT
modes
STOP mode
Note:
System Reset
A POR/VBO event always has priority over all other possible reset sources to insure a full
system reset occurs.
During a System Reset, a Z8 Encore! XP
cycles of the WDT oscillator followed by 16 cycles of the system clock. At the beginning
of Reset, all GPIO pins are configured as inputs. All GPIO programmable pull-ups are dis-
abled.
During Reset, the eZ8 CPU and the on-chip peripherals are idle; however, the on-chip
crystal oscillator and WDT oscillator continue to run. The system clock begins operating
following the WDT oscillator cycle count. The eZ8 CPU and on-chip peripherals remain
idle through all the 16 cycles of the system clock.
Upon Reset, control registers within the Register File which have a defined Reset value
are loaded with their reset values. Other control registers (including the Stack Pointer,
Register Pointer, and Flags) and general-purpose RAM are undefined following the Reset.
The eZ8 CPU fetches the Reset vector at Program Memory addresses
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address.
Table 9
provides more detailed information on the individual reset sources.
Reset Source
POR/VBO
WDT time-out
when configured for Reset
RESET pin assertion
OCD initiated Reset
(OCDCTL[0] set to 1)
POR/ VBO
RESET pin assertion
DBG pin driven Low
lists the reset sources as a function of the operating mode. The text following
Reset Type
System Reset
System Reset
System Reset
System Reset except the OCD is unaffected by the
reset
System Reset
System Reset
System Reset
®
F0822 Series device is held in Reset for 66
Z8 Encore! XP
Reset and Stop Mode Recovery
Product Specification
0002H
®
F0822 Series
and
0003H
40