Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 186
Z8F042AHH020EG
Manufacturer Part Number
Z8F042AHH020EG
Description
IC ENCORE XP MCU FLASH 4K 20SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F08200100KIT.pdf
(264 pages)
Specifications of Z8F042AHH020EG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4156
Z8F042AHH020EG
Z8F042AHH020EG
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PS022517-0508
START
Debug Mode
OCD Data Format
The operating characteristics of the Z8 Encore! XP
mode are:
•
•
•
•
•
Entering Debug Mode
The device enters DEBUG mode following any of the following operations:
•
•
•
•
•
Exiting Debug Mode
The device exits DEBUG mode following any of the following operations:
•
•
•
•
•
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1
Figure
D0
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to
execute specific instructions.
The system clock operates unless in STOP mode.
All enabled on-chip peripherals operate unless in STOP mode.
Automatically exits HALT mode.
Constantly refreshes the Watchdog Timer, if enabled.
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface.
eZ8 CPU execution of a BRK (Breakpoint) instruction.
Match of PC to OCDCNTR register (when enabled)
OCDCNTR register decrements to 0000H (when enabled)
If the
device into DEBUG mode.
Clearing the DBGMODE bit in the OCD Control Register to 0.
Power-On Reset
Voltage Brownout reset
Asserting the
Driving the
40).
DBG
D1
pin is Low when the device exits Reset, the OCD automatically puts the
DBG
RESET
Figure 40. OCD Data Format
pin Low while the device is in STOP mode initiates a System Reset.
D2
pin Low to initiate a Reset.
D3
D4
®
D5
F0822 Series devices in DEBUG
Z8 Encore! XP
D6
Product Specification
STOP
D7
®
On-Chip Debugger
F0822 Series
bit (see
STOP
173
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