Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 111

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

PS022517-0508
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
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•
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UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data Register. The break detect and overrun status bits are not
displayed until the valid data is read.
After the valid data has been read, the UART Status 0 Register is updated to indicate the
overrun condition (and Break Detect, if applicable). The
the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte cannot contain valid data and should be ignored. The
cates if the overrun was caused by a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data Register must be read again to clear the
error bits is the UART Status 0 Register. Updates to the Receive Data Register occur only
when the next data word is received.
UART Data and Error Handling Procedure
Figure16
Baud Rate Generator Interrupts
If the BRG interrupt enable is set, the UART Receiver interrupt asserts when the UART
Baud Rate Generator reloads. This action allows the BRG to function as an additional
counter if the UART functionality is not employed.
A data byte is received and is available in the UART Receive Data Register. This
interrupt can be disabled independent of the other receiver interrupt sources. The
received data interrupt occurs once the receive character is received and placed in the
Receive Data Register. Software must respond to this received data available
condition before the next character is completely received to avoid an overrun error. In
MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte
A break is received
An overrun is detected
A data framing error is detected
on page 99 displays the recommended procedure for UART receiver ISRs.
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP
RDA
bit is set to 1 to indicate that
Product Specification
®
BRKD
F0822 Series
bit indi-
98