Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 149

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

PS022517-0508
Read Transaction with a 7-Bit Address
17. The I
18. If more bytes remain to be sent, return to
19. If the last byte is currently being sent, software sets the STOP bit of the I
20. The I
21. The slave can either Acknowledge or Not Acknowledge the last byte. Because either
22. The I
Figure 30
The shaded regions indicate data transferred from the I
unshaded regions indicate data transferred from the slaves to the I
Follow the steps below for a read operation to a 7-bit addressed slave:
1. Software writes the I
2. Software asserts the START bit of the I
3. If this is a single byte transfer, Software asserts the NAK bit of the I
4. The I
5. The I
6. If the I
S
I
Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH
bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus
and clears the STOP and NCKI bits. The transaction is complete (ignore the following
steps).
Transmit Interrupt is asserted.
Register (or START bit to initiate a new transaction). In the STOP case, software also
clears the TXI bit of the I
the STOP or START bit is already set, the NCKI interrupt does not occur.
the STOP (or START) bit.
so that after the first byte of data has been read by the I
Acknowledge is sent to the I
next high period of SCL, the I
Continue with
2
C Controller sets the NCKI bit and clears the ACK bit in the I
Figure 30. Receive Data Transfer Format for a 7-Bit Addressed Slave
2
2
2
2
2
C Controller sends the STOP (or RESTART) condition to the I
displays the data transfer format for a read operation to a 7-bit addressed slave.
C Controller shifts the data out by the SDA signal. After the first bit is sent, the
C Controller completes transmission of the last data byte on the SDA signal.
C Controller sends the START condition.
C Controller shifts the address and read bit out the SDA signal.
2
Slave Address
C Slave acknowledges the address by pulling the SDA signal Low during the
step
7.
2
C Data Register with a 7-bit Slave address plus the read bit (=1).
2
C Control Register at the same time.
2
C Slave.
2
C Controller sets the ACK bit in the I
R = 1
2
C Control Register.
step
A
14.
Data
2
Z8 Encore! XP
C Controller to slaves and
2
C Controller, a Not
A
Product Specification
2
C Controller.
2
C Status register.
Data
2
C Control Register
2
2
®
C Status register.
C bus and clears
F0822 Series
2
I2C Controller
C Control
A
P/S
136