Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 76

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

Table 27. Interrupt Request 2 Register (IRQ2)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
Interrupt Request 2 Register
IRQ0 Enable High and Low Bit Registers
7
The Interrupt Request 2 (IRQ2) Register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU.
If interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the IRQ2
Register to determine if any interrupt requests are pending.
Reserved—Must be 0
PCxI—Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Where x indicates the specific GPIO Port C pin number (0 through 3).
The IRQ0 Enable High and Low Bit Registers
encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated
by setting bits in each register.
Table 28. IRQ0 Enable and Priority Encoding
where x indicates the register bits from 0 through 7.
IRQ0ENH[x]
6
0
0
1
1
Reserved
IRQ0ENL[x]
5
0
1
0
1
4
Table 28
Priority
Disabled
Level 1
Level 2
Level 3
FC6H
R/W
describes the priority control for IRQ0.
(Table
0
3
PC3I
(Table 29
27) stores interrupt requests for both
Description
Disabled
Low
Nominal
High
2
Z8 Encore! XP
and
PC2I
Table
Product Specification
1
30) form a priority
PC1I
®
Interrupt Controller
F0822 Series
0
PC0I
63