Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 150

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

PS022517-0508
S
Slave Address
Read Transaction with a 10-Bit Address
1st 7 bits
7. The I
8. The I
9. Software responds by reading the I
10. If there are more bytes to transfer, return to Step 7.
11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I
12. Software responds by setting the STOP bit of the I
13. A STOP condition is sent to the I
Figure 31
regions indicate data transferred from the I
indicate data transferred from the slaves to the I
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Follow the steps below for the data transfer procedure for a read operation to a 10-bit
addressed slave:
1. Software writes
2. Software asserts the START and TXI bits of the I
3. The I
4. The I
Figure 31. Receive Data Format for a 10-Bit Addressed Slave
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP bit and clearing the TXI bit. The I2C
Controller sends the STOP condition on the bus and clears the STOP and NCKI bits.
The transaction is complete (ignore the following steps).
The I
(last byte), else it sends an Acknowledge.
there is only one more byte to receive, set the NAK bit of the I
Controller.
Data Register.
Register.
W=0 A
2
2
2
2
2
displays the read transaction format for a 10-bit addressed slave. The shaded
C Controller shifts in the byte of data from the I
C Controller sends a Not Acknowledge to the I
C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
C Controller sends the Start condition.
C Controller loads the I
Slave Address
11110B
2nd Byte
followed by the two address bits and a 0 (write) to the I
2
C Shift register with the contents of the I
A S
2
C Slave, the STOP and NCKI bits are cleared.
2
C Data Register which clears the RDRF bit. If
2
Slave Address
C Controller to slaves and unshaded regions
1st 7 bits
2
C Controller.
11110XX
2
C Control Register.
2
C Control Register.
Z8 Encore! XP
2
2
C Slave if the NAK bit is set
C Slave on the SDA signal.
. The two bits
R=1 A Data A Data A P
Product Specification
2
C Control Register.
®
F0822 Series
XX
2
C Data
I2C Controller
are the two
2
2
C
C
137