Z8F042AHH020EG Zilog, Z8F042AHH020EG Datasheet - Page 195

• Manufacturer Part Number: Z8F042AHH020EG
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4156; Z8F042AHH020EG

Table 94. OCD Control Register (OCDCTL)
BITS
FIELD
RESET
R/W
PS022517-0508
DBGMODE
7
A “reset and stop” function can be achieved by writing
go” function can be achieved by writing
mode, a “run” function can be implemented by writing
DBGMODE—Debug Mode
Setting this bit to 1 causes the device to enter DEBUG mode. When in DEBUG mode, the
eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to start
running again. This bit is automatically set when a BRK instruction is decoded and Break-
points are enabled. If the Read Protect Option Bit is enabled, this bit can only be cleared
by resetting the device, it cannot be written to 0.
0 = The Z8 Encore! XP F0822 Series device is operating in NORMAL mode.
1 = The Z8 Encore! XP F0822 Series device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode
points are disabled and the BRK instruction behaves like an NOP instruction. If this bit is
set to 1 and a BRK instruction is decoded, the OCD takes action dependent upon the BRK-
LOOP bit.
0 = BRK instruction is disabled.
1 = BRK instruction is enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
an Debug Acknowledge character (
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
BRKLOOP—Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded if
breakpoints are enabled (BRKEN is 1). If this bit is 0, then the DBGMODE bit is automat-
ically set to 1 and the OCD enter DEBUG mode. If BRKLOOP is set to 1, then the eZ8
CPU loops on the BRK instruction.
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
BRKPC—Break when PC == OCDCNTR
If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR register, DBGMODE is
BRKEN
R/W
6
DBGACK BRKLOOP
5
FFH
4
) to the host when a Breakpoint occurs.
41H
0
to this register. If the device is in DEBUG
BRKPC
3
R
40H
81H
Z8 Encore! XP
BRKZRO
to this register.
to this register. A “reset and
2
00H
Product Specification
). By default, Break-
Reserved
®
1
On-Chip Debugger
F0822 Series
RST
R/W
0
182