C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 11

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13. Reset Sources
14. Oscillators
15. Flash Memory
16. Branch Target Cache
17. External Data Memory Interface and On-Chip XRAM
18. Port Input/Output
19. System Management Bus / I2C Bus (SMBus0)
20. Enhanced Serial Peripheral Interface (SPI0)
Figure 13.1. Reset Sources.................................................................................... 177
Figure 13.2. Reset Timing ...................................................................................... 178
Figure 14.1. Oscillator Diagram.............................................................................. 185
Figure 14.2. PLL Block Diagram............................................................................. 191
Figure 15.1. Flash Memory Map for MOVC Read and MOVX Write Operations ... 201
Figure 15.2. 128 kB Flash Memory Map and Security Bytes ................................. 204
Figure 15.3. 64 kB Flash Memory Map and Security Bytes ................................... 205
Figure 16.1. Branch Target Cache Data Flow ........................................................ 211
Figure 16.2. Branch Target Cache Organiztion...................................................... 212
Figure 16.3. Cache Lock Operation........................................................................ 214
Figure 17.1. Multiplexed Configuration Example.................................................... 222
Figure 17.2. Non-multiplexed Configuration Example ............................................ 223
Figure 17.3. EMIF Operating Modes ...................................................................... 224
Figure 17.4. Non-multiplexed 16-bit MOVX Timing ................................................ 227
Figure 17.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 228
Figure 17.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 229
Figure 17.7. Multiplexed 16-bit MOVX Timing........................................................ 230
Figure 17.8. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 231
Figure 17.9. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 232
Figure 18.1. Port I/O Cell Block Diagram ............................................................... 235
Figure 18.2. Port I/O Functional Block Diagram ..................................................... 237
Figure 18.3. Priority Crossbar Decode Table (EMIFLE = 0; P1MDIN = 0xFF)....... 238
Figure 18.4. Priority Crossbar Decode Table
Figure 18.5. Priority Crossbar Decode Table
Figure 18.6. Crossbar Example.............................................................................. 244
Figure 19.1. SMBus0 Block Diagram ..................................................................... 259
Figure 19.2. Typical SMBus Configuration ............................................................. 260
Figure 19.3. SMBus Transaction ............................................................................ 261
Figure 19.4. Typical Master Transmitter Sequence................................................ 262
Figure 19.5. Typical Master Receiver Sequence.................................................... 262
Figure 19.6. Typical Slave Transmitter Sequence.................................................. 263
Figure 19.7. Typical Slave Receiver Sequence...................................................... 263
Figure 20.1. SPI Block Diagram ............................................................................. 273
Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 276
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 276
(EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xFF) ................ 241
(EMIFLE = 1; EMIF in Non-Multiplexed Mode; P1MDIN = 0xFF) ........ 242
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
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