C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 177

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pullups during and after the
reset. For V
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator running at its lowest frequency. Refer to Section “
tion on selecting and configuring the system clock source. The Watchdog Timer is enabled using its
longest timeout interval (see Section “
source is stable, program execution begins at location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on, power-fail, external RST pin,
external CNVSTR0 signal, software command, Comparator0, Missing Clock Detector, and Watchdog
Timer. Each reset source is described in the following sections.
CIP-51 halts program execution.
Special Function Registers (SFRs) are initialized to their defined reset values.
External port pins are forced to a known configuration.
Interrupts and timers are disabled.
(Port
XTAL1
XTAL2
DD
I/O)
CP0+
CP0-
Monitor resets, the RST pin is driven low until the end of the V
Generator
Circuitry
Internal
Clock
OSC
Crossbar
PLL
Comparator0
CNVSTR
+
-
(CNVSTR
enable)
reset
enable)
Figure 13.1. Reset Sources
(CP0
reset
Clock Select
System
Clock
13.7. Watchdog Timer Reset
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
Rev. 1.4
VDD
Handler
Core
EN
WDT
C8051F120/1/2/3/4/5/6/7
PRE
Supply
Monitor
+
-
Software Reset
System Reset
14. Oscillators
Timeout
Supply
Reset
” on page
C8051F130/1/2/3
(wired-OR)
DD
179
Reset
Funnel
” on page
reset timeout.
). Once the system clock
185
/RST
for informa-
177