C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 167

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.3. Operating in Multiply and Accumulate Mode
MAC0 operates in Multiply and Accumulate (MAC) mode when the MAC0MS bit (MAC0CF.0) is cleared to
‘0’. When operating in MAC mode, MAC0 performs a 16-by-16 bit multiply on the contents of the MAC0A
and MAC0B registers, and adds the result to the contents of the 40-bit MAC0 accumulator. Figure 12.4
shows the MAC0 pipeline. There are three stages in the pipeline, each of which takes exactly one SYS-
CLK cycle to complete. The MAC operation is initiated with a write to the MAC0BL register. After the
MAC0BL register is written, MAC0A and MAC0B are multiplied on the first SYSCLK cycle. During the sec-
ond stage of the MAC0 pipeline, the results of the multiplication are added to the current accumulator con-
tents, and the result of the addition is stored in the MAC0 accumulator. The status flags in the MAC0STA
register are set after the end of the second pipeline stage. During the second stage of the pipeline, the next
multiplication can be initiated by writing to the MAC0BL register, if it is desired. The rounded (and option-
ally, saturated) result is available in the MAC0RNDH and MAC0RNDL registers at the end of the third pipe-
line stage. If the MAC0CA bit (MAC0CF.3) is set to ‘1’ when the MAC operation is initiated, the accumulator
and all MAC0STA flags will be cleared during the next cycle of the controller’s clock (SYSCLK). The
MAC0CA bit will clear itself to ‘0’ when the clear operation is complete.
12.4. Operating in Multiply Only Mode
MAC0 operates in Multiply Only mode when the MAC0MS bit (MAC0CF.0) is set to ‘1’. Multiply Only mode
is identical to Multiply and Accumulate mode, except that the multiplication result is added with a value of
zero before being stored in the MAC0 accumulator (i.e. it overwrites the current accumulator contents).
The result of the multiplication is available in the MAC0 accumulator registers at the end of the second
MAC0 pipeline stage (two SYSCLKs after writing to MAC0BL). As in MAC mode, the rounded result is
available in the MAC0 Rounding Registers after the third pipeline stage. Note that in Multiply Only mode,
the MAC0HO flag is not affected.
12.5. Accumulator Shift Operations
MAC0 contains a 1-bit arithmetic shift function which can be used to shift the contents of the 40-bit accu-
mulator left or right by one bit. The accumulator shift is initiated by writing a ‘1’ to the MAC0SC bit
(MAC0CF.5), and takes one SYSCLK cycle (the rounded result is available in the MAC0 Rounding Regis-
ters after a second SYSCLK cycle, and MAC0SC is cleared to ‘0’). The direction of the arithmetic shift is
controlled by the MAC0SD bit (MAC0CF.4). When this bit is cleared to ‘0’, the MAC0 accumulator will shift
left. When the MAC0SD bit is set to ‘1’, the MAC0 accumulator will shift right. Right-shift operations are
sign-extended with the current value of bit 39. Note that the status flags in the MAC0STA register are not
affected by shift operations.
MAC0BL
MAC0 Operation
Write
Begins
Multiply
Figure 12.4. MAC0 Pipeline
Operation May
Next MAC0
Be Initiated
MAC0BL
Results Available
Write
Here
Add
Accumulator
Rev. 1.4
Multiply
Round
C8051F120/1/2/3/4/5/6/7
Rounded Results
Add
Available
C8051F130/1/2/3
Round
167