C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 143

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Bits7–0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in
Bits7–0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in
R/W
R/W
Bit7
Bit7
a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFR-
LAST is the third entry. The SFR stack bytes may be used alter the context in the SFR Page
Stack, and will not cause the stack to ‘push’ or ‘pop’. Only interrupts and return from inter-
rupts cause pushes and pops of the SFR Page Stack.
Write: Sets the SFR Page contained in the second byte of the SFR Stack. This will cause
the SFRPAGE SFR to have this SFR page value upon a return from interrupt.
Read: Returns the value of the SFR page contained in the second byte of the SFR stack.
This is the value that will go to the SFR Page register upon a return from interrupt.
a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFR-
LAST is the third entry. The SFR stack bytes may be used alter the context in the SFR Page
Stack, and will not cause the stack to ‘push’ or ‘pop’. Only interrupts and return from inter-
rupts cause pushes and pops of the SFR Page Stack.
Write: Sets the SFR Page in the last entry of the SFR Stack. This will cause the SFRNEXT
SFR to have this SFR page value upon a return from interrupt.
Read: Returns the value of the SFR page contained in the last entry of the SFR stack.
R/W
R/W
Bit6
Bit6
SFR Definition 11.4. SFRNEXT: SFR Next Register
SFR Definition 11.5. SFRLAST: SFR Last Register
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
Rev. 1.4
R/W
R/W
Bit3
Bit3
C8051F120/1/2/3/4/5/6/7
R/W
R/W
Bit2
Bit2
C8051F130/1/2/3
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
R/W
Bit0
R/W
Bit0
0x85
All Pages
00000000
Reset Value
0x86
All Pages
00000000
Reset Value
143