C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 168

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
12.6. Rounding and Saturation
A Rounding Engine is included, which can be used to provide a rounded result when operating on frac-
tional numbers. MAC0 uses an unbiased rounding algorithm to round the data stored in bits 31 – 16 of the
accumulator, as shown in Table 12.1. Rounding occurs during the third stage of the MAC0 pipeline, after
any shift operation, or on a write to the LSB of the accumulator. The rounded results are stored in the
rounding registers: MAC0RNDH (SFR Definition 12.12) and MAC0RNDL (SFR Definition 12.13). The
accumulator registers are not affected by the rounding engine. Although rounding is primarily used for frac-
tional data, the data in the rounding registers is updated in the same way when operating in integer mode.
The rounding engine can also be used to saturate the results stored in the rounding registers. If the
MAC0SAT bit is set to ‘1’ and the rounding register overflows, the rounding registers will saturate. When a
positive overflow occurs, the rounding registers will show a value of 0x7FFF when saturated. For a nega-
tive overflow, the rounding registers will show a value of 0x8000 when saturated. If the MAC0SAT bit is
cleared to ‘0’, the rounding registers will not saturate.
12.7. Usage Examples
This section details some software examples for using MAC0.
operations using fractional numbers.
integer numbers. The last example, shown in
shift operations can be used to modify the accumulator. All of the examples assume that all of the flags in
the MAC0STA register are initially set to ‘0’.
12.7.1. Multiply and Accumulate Example
The example below implements the equation:
MOV
MOV
MOV
MOV
MOV
MOV
MOV
NOP
NOP
NOP
168
Accumulator Bits 15–0
(MAC0ACC1:MAC0ACC0)
Greater Than 0x8000
Less Than 0x8000
Equal To 0x8000
Equal To 0x8000
MAC0CF, #0Ah
MAC0AH, #40h
MAC0AL, #00h
MAC0BH, #20h
MAC0BL, #00h
MAC0BH, #E0h
MAC0BL, #00h
Table 12.1. MAC0 Rounding (MAC0SAT = 0)
; Set to Clear Accumulator, Use fractional numbers
; Load MAC0A register with 4000 hex = 0.5 decimal
; Load MAC0B register with 2000 hex = 0.25 decimal
; This line initiates the first MAC operation
; Load MAC0B register with E000 hex = -0.25 decimal
; This line initiates the second MAC operation
; After this instruction, the Accumulator should be equal to 0,
; and the MAC0STA register should be 0x04, indicating a zero
; After this instruction, the Rounding register is updated
Accumulator Bits 31–16
(MAC0ACC3:MAC0ACC2)
Anything
Anything
Odd (LSB = 1)
Even (LSB = 0)

0.5 0.25

Section 12.7.2

+

0.5
Section 12.7.3

–
Rev. 1.4
0.25
shows a single operation in Multiply Only mode with

=
0.125 0.125
Rounding
Direction
Up
Down
Up
Down
, demonstrates how the left-shift and right-
–
Section 12.7.1
=
0.0
Rounded Results
(MAC0RNDH:MAC0RNDL)
(MAC0ACC3:MAC0ACC2) + 1
(MAC0ACC3:MAC0ACC2)
(MAC0ACC3:MAC0ACC2) + 1
(MAC0ACC3:MAC0ACC2)
shows a series of two MAC