C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 110

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
110
Bit7:
Bits6–5: UNUSED. Read = 00b; Write = don’t care.
Bits4–3: DAC1MD1–0: DAC1 Mode Bits:
Bits2–0: DAC1DF2: DAC1 Data Format Bits:
DAC1EN
MSB
R/W
Bit7
MSB
DAC1EN: DAC1 Enable Bit.
0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode.
1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational.
00: DAC output updates occur on a write to DAC1H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
000:
001:
010:
011:
1xx:
MSB
R/W
Bit6
-
The most significant nibble of the DAC1 Data Word is in DAC1H[3:0], while the least
significant byte is in DAC1L.
The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least
significant 7-bits are in DAC1L[7:1].
The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least
significant 6-bits are in DAC1L[7:2].
The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least
significant 5-bits are in DAC1L[7:3].
The most significant 8-bits of the DAC1 Data Word is in DAC1H[7:0], while the least
significant 4-bits are in DAC1L[7:4].
MSB
DAC1H
DAC1H
DAC1H
DAC1H
DAC1H
SFR Definition 8.6. DAC1CN: DAC1 Control
R/W
Bit5
MSB
-
DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 00000000
R/W
Bit4
Rev. 1.4
R/W
Bit3
R/W
Bit2
LSB
R/W
Bit1
DAC1L
DAC1L
DAC1L
DAC1L
DAC1L
LSB
SFR Address:
SFR Page:
R/W
Bit0
LSB
LSB
0xD4
1
Reset Value
LSB