C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 113

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
9.
Voltage Reference
The voltage reference options available on the C8051F12x and C8051F13x device families vary according
to the device capabilities.
All devices include an internal voltage reference circuit, consisting of a 1.2 V, 15 ppm/°C (typical) bandgap
voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed
via the VREF pin to external system components or to the voltage reference input pins. The maximum load
seen by the VREF pin must be less than 200 µA to AGND. Bypass capacitors of 0.1 µF and 4.7 µF are rec-
ommended from the VREF pin to AGND.
The Reference Control Register, REF0CN enables/disables the internal reference generator and the inter-
nal temperature sensor on all devices. The BIASE bit in REF0CN enables the on-board reference genera-
tor while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When
disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and
the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the ref-
erence voltage generator, BIASE and REFBE must both be set to logic 1. If the internal reference is not
used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if any DACs or ADCs are
used, regardless of whether the voltage reference is derived from the on-chip reference or supplied by an
off-chip source. If no ADCs or DACs are being used, both of these bits can be set to logic 0 to conserve
power.
When enabled, the temperature sensor connects to the highest order input of the ADC0 input multiplexer.
The TEMPE bit within REF0CN enables and disables the temperature sensor. While disabled, the temper-
ature sensor defaults to a high impedance state. Any ADC measurements performed on the sensor while
disabled will result in undefined data.
The electrical specifications for the internal voltage reference are given in Table 9.1.
9.1.
Reference Configuration on the C8051F120/2/4/6
On the C8051F120/2/4/6 devices, the REF0CN register also allows selection of the voltage reference
source for ADC0 and ADC2, as shown in SFR Definition 9.1. Bits AD0VRS and AD2VRS in the REF0CN
register select the ADC0 and ADC2 voltage reference sources, respectively. Three voltage reference input
pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage
reference output (with an external connection). ADC0 may also reference the DAC0 output internally, and
ADC2 may reference the analog power supply voltage, via the VREF multiplexers shown in Figure 9.1.
Rev. 1.4
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