C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 264

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
19.4. SMBus Special Function Registers
The SMBus0 serial interface is accessed and controlled through five SFR’s: SMB0CN Control Register,
SMB0CR Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Sta-
tus Register. The five special function registers related to the operation of the SMBus0 interface are
described in the following sections.
19.4.1. Control Register
The SMBus0 Control register SMB0CN is used to configure and control the SMBus0 interface. All of the
bits in the register can be read or written by software. Two of the control bits are also affected by the
SMBus0 hardware. The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by the hardware when a valid
serial interrupt condition occurs. It can only be cleared by software. The Stop flag (STO, SMB0CN.4) is set
to logic 1 by software. It is cleared to logic 0 by hardware when a STOP condition is detected on the bus.
Setting the ENSMB flag to logic 1 enables the SMBus0 interface. Clearing the ENSMB flag to logic 0 dis-
ables the SMBus0 interface and removes it from the bus. Momentarily clearing the ENSMB flag and then
resetting it to logic 1 will reset SMBus0 communication. However, ENSMB should not be used to tempo-
rarily remove a device from the bus since the bus state information will be lost. Instead, the Assert
Acknowledge (AA) flag should be used to temporarily remove the device from the bus (see description of
AA flag below).
Setting the Start flag (STA, SMB0CN.5) to logic 1 will put SMBus0 in a master mode. If the bus is free,
SMBus0 will generate a START condition. If the bus is not free, SMBus0 waits for a STOP condition to free
the bus and then generates a START condition after a 5 µs delay per the SMB0CR value (In accordance
with the SMBus protocol, the SMBus0 interface also considers the bus free if the bus is idle for 50 µs and
no STOP condition was recognized). If STA is set to logic 1 while SMBus0 is in master mode and one or
more bytes have been transferred, a repeated START condition will be generated.
When the Stop flag (STO, SMB0CN.4) is set to logic 1 while the SMBus0 interface is in master mode, the
interface generates a STOP condition. In a slave mode, the STO flag may be used to recover from an error
condition. In this case, a STOP condition is not generated on the bus, but the SMBus hardware behaves
as if a STOP condition has been received and enters the "not addressed" slave receiver mode. Note that
this simulated STOP will not cause the bus to appear free to SMBus0. The bus will remain occupied until a
STOP appears on the bus or a Bus Free Timeout occurs. Hardware automatically clears the STO flag to
logic 0 when a STOP condition is detected on the bus.
The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by hardware when the SMBus0 interface enters
one of 27 possible states. If interrupts are enabled for the SMBus0 interface, an interrupt request is gener-
ated when the SI flag is set. The SI flag must be cleared by software.
Important Note: If SI is set to logic 1 while the SCL line is low, the clock-low period of the serial clock will
be stretched and the serial transfer is suspended until SI is cleared to logic 0. A high level on SCL is not
affected by the setting of the SI flag.
The Assert Acknowledge flag (AA, SMB0CN.2) is used to set the level of the SDA line during the acknowl-
edge clock cycle on the SCL line. Setting the AA flag to logic 1 will cause an ACK (low level on SDA) to be
sent during the acknowledge cycle if the device has been addressed. Setting the AA flag to logic 0 will
cause a NACK (high level on SDA) to be sent during acknowledge cycle. After the transmission of a byte in
slave mode, the slave can be temporarily removed from the bus by clearing the AA flag. The slave's own
address and general call address will be ignored. To resume operation on the bus, the AA flag must be
reset to logic 1 to allow the slave's address to be recognized.
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