C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 216

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
216
Bits 7–4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4–1).
Bit 3:
Bit 2:
Bits 1–0: CHMSTH: Cache Miss Penalty Threshold.
Bit 7:
Bit 6:
Bits 5–0: CHSLOT: Cache Slot Pointer.
CHPUSH
R/W
R/W
Bit7
Bit7
These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first
be latched by reading the CHMSCTH bits in the CCH0MA Register (See SFR Definition
16.4).
CHALGM: Cache Algorithm Select.
This bit selects the cache replacement algorithm.
0: Cache uses Rebound algorithm.
1: Cache uses Pseudo-random algorithm.
CHFIXM: Cache Fix MOVC Enable.
This bit forces MOVC writes to the cache memory to use slot 0.
0: MOVC data is written according to the current algorithm selected by the CHALGM bit.
1: MOVC data is always written to cache slot 0.
These bits determine when missed instruction data will be cached.
If data takes longer than CHMSTH clocks to obtain, it will be cached.
CHPUSH: Cache Push Enable.
This bit enables cache push operations, which will lock information in cache slots using
MOVC instructions.
0: Cache push operations are disabled.
1: Cache push operations are enabled. When a MOVC read is executed, the requested 4-
byte segment containing the data is locked into the cache at the location indicated by
CHSLOT, and CHSLOT is decremented.
Note that no more than 61 cache slots should be locked at one time, since the entire cache
will be unlocked when CHSLOT is equal to 0.
CHPOP: Cache Pop.
Writing a ‘1’ to this bit will increment CHSLOT and then unlock that location. This bit always
reads ‘0’. Note that Cache Pop operations should not be performed while CHSLOT =
111110b. “Pop”ing more Cache slots than have been “Push”ed will have indeterminate
results on the Cache performance.
These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are
locked, and will not be changed by the processor, except when CHSLOT equals 0.
CHPOP
R/W
R/W
Bit6
Bit6
CHMSCTL
SFR Definition 16.3. CCH0LC: Cache Lock Control
SFR Definition 16.2. CCH0TN: Cache Tuning
R/W
Bit5
Bit5
R
R/W
Bit4
Bit4
R
CHALGM CHFIXM
Rev. 1.4
R/W
Bit3
Bit3
R
CHSLOT
R/W
Bit2
Bit2
R
R/W
Bit1
Bit1
R
CHMSTH
SFR Address:
SFR Address:
SFR Page:
SFR Page:
R/W
Bit0
Bit0
R
0xA2
F
0xA3
F
00000100
Reset Value
Reset Value
00111110