C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 202

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
15.1.3. Writing Flash Memory From Software
Bytes in Flash memory can be written one byte at a time, or in small blocks. The CHBLKW bit in register
CCH0CN (SFR Definition 16.1) controls whether a single byte or a block of bytes is written to Flash during
a write operation. When CHBLKW is cleared to ‘0’, the Flash will be written one byte at a time. When
CHBLKW is set to ‘1’, the Flash will be written in blocks of four bytes for addresses in code space, or
blocks of two bytes for addresses in the Scratchpad area. Block writes are performed in the same amount
of time as single byte writes, which can save time when storing large amounts of data to Flash memory.
For single-byte writes to Flash, bytes are written individually, and the Flash write is performed after each
MOVX write instruction. The recommended procedure for writing Flash in single bytes is as follows:
For block Flash writes, the Flash write procedure is only performed after the last byte of each block is writ-
ten with the MOVX write instruction. When writing to addresses located in any of the four code banks, a
Flash write block is four bytes long, from addresses ending in 00b to addresses ending in 11b. Writes must
be performed sequentially (i.e. addresses ending in 00b, 01b, 10b, and 11b must be written in order). The
Flash write will be performed following the MOVX write that targets the address ending in 11b. When writ-
ing to addresses located in the Flash Scratchpad area, a Flash block is two bytes long, from addresses
ending in 0b to addresses ending in 1b. The Flash write will be performed following the MOVX write that
targets the address ending in 1b. If any bytes in the block do not need to be updated in Flash, they should
be written to 0xFF. The recommended procedure for writing Flash in blocks is as follows:
202
Step 1. Disable interrupts.
Step 2. Clear CHBLKW (CCH0CN.0) to select single-byte write mode.
Step 3. If writing to bytes in Bank 1, Bank 2, or Bank 3, set the COBANK bits (PSBANK.5-4) for
Step 4. If writing to bytes in the Scratchpad area, set the SFLE bit (PSCTL.2).
Step 5. Set FLWE (FLSCL.0) to enable Flash writes/erases via user software.
Step 6. Set PSWE (PSCTL.0) to redirect MOVX commands to write to Flash.
Step 7. Use the MOVX instruction to write a data byte to the desired location (repeat as
Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space.
Step 9. Clear the FLWE bit, to disable Flash writes/erases.
Step 10. If writing to bytes in the Scratchpad area, clear the SFLE bit.
Step 11. Re-enable interrupts.
Step 1. Disable interrupts.
Step 2. Set CHBLKW (CCH0CN.0) to select block write mode.
Step 3. If writing to bytes in Bank 1, Bank 2, or Bank 3, set the COBANK bits (PSBANK.5-4) for
Step 4. If writing to bytes in the Scratchpad area, set the SFLE bit (PSCTL.2).
Step 5. Set FLWE (FLSCL.0) to enable Flash writes/erases via user software.
Step 6. Set PSWE (PSCTL.0) to redirect MOVX commands to write to Flash.
Step 7. Use the MOVX instruction to write data bytes to the desired block. The data bytes must
Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space.
Step 9. Clear the FLWE bit, to disable Flash writes/erases.
Step 10. If writing to bytes in the Scratchpad area, clear the SFLE bit.
Step 11. Re-enable interrupts.
the appropriate bank.
necessary).
the appropriate bank.
be written sequentially, and the last byte written must be the high byte of the block (see
text for details, repeat as necessary).
Rev. 1.4