C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 155

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.3.2. External Interrupts
Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or
active-low edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0
(TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts,
respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin.
The external interrupt source must hold the input active until the interrupt request is recognized. It must
then deactivate the interrupt request before execution of the ISR completes or another interrupt request
will be generated.
Interrupt Source
Reset
External Interrupt 0 (/INT0) 0x0003
Timer 0 Overflow
External Interrupt 1 (/INT1) 0x0013
Timer 1 Overflow
UART0
Timer 2
Serial Peripheral Interface 0x0033
SMBus Interface
ADC0 Window Comparator 0x0043
Programmable Counter
Array
Comparator 0 Falling Edge 0x0053
Comparator 0 Rising Edge 0x005B
Comparator 1 Falling Edge 0x0063
0x000B
0x001B
0x002B
0x003B
0x004B
0x0000
0x0023
Interru
Vector
pt
Table 11.4. Interrupt Summary
Priority
Order
Top
10
11
12
0
1
2
3
4
5
6
7
8
9
Pending Flags
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2 (TMR2CN.7)
EXF2 (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.3)
AD0WINT
(ADC0CN.1)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
N/A N/A 0
C8051F130/1/2/3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
0 EX0 (IE.0) PX0 (IP.0)
0 ET0 (IE.1) PT0 (IP.1)
0 EX1 (IE.2) PX1 (IP.2)
0 ET1 (IE.3) PT1 (IP.3)
0 ES0 (IE.4) PS0 (IP.4)
0 ET2 (IE.5) PT2 (IP.5)
0
0
0
1
2
0
1
Always
Enabled
Enable
Flag
ESPI0
(EIE1.0)
ESMB0
(EIE1.1)
EWADC0
(EIE1.2)
EPCA0
(EIE1.3)
ECP0F
(EIE1.4)
ECP0R
(EIE1.5)
ECP1F
(EIE1.6)
Priority
Control
Always
Highest
PSPI0
(EIP1.0)
PSMB0
(EIP1.1)
PWADC0
(EIP1.2)
PPCA0
(EIP1.3)
PCP0F
(EIP1.4)
PCP0R
(EIP1.5)
PCP1F
(EIP1.6)
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