C8051F120-GQR Silicon Laboratories Inc, C8051F120-GQR Datasheet - Page 261

• Manufacturer Part Number: C8051F120-GQR
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F120-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 19.3 illustrates a typical
SMBus transaction.
19.2.1. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see
attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give
up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a
LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect
a LOW SDA and give up the bus. The winning master continues its transmission without interruption; the
losing master becomes a slave and receives the rest of the transfer. This arbitration scheme is non-
destructive: one device always wins, and no data is lost.
19.2.2. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
19.2.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
19.2.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. If an SMBus device is waiting to generate a Master START, the START will be gen-
erated following the bus free timeout.
SCL
SDA
START
SLA6
Slave Address + R/W
Figure 19.3. SMBus Transaction
SLA5-0
R/W
Rev. 1.4
Section 19.2.4
ACK
C8051F120/1/2/3/4/5/6/7
D7
). In the event that two or more devices
Data Byte
C8051F130/1/2/3
D6-0
NACK
STOP
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