HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 126

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

5.5
5.5.1
Specific cache entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the
address tag specified by the write data is compared to the address tag within the cache selected by
the entry address, and data is written when a match is found. If no match is found, there is no
operation. R0 specifies the write data in R0 and R1 specifies the address. When the V bit of an
entry in the address array is set to 0, the entry is written back if the entry’s U bit is 1.
5.5.2
This example reads the data section of a specific cache entry. The longword indicated in the data
field of the data array in figure 5.5 is read to the register. R0 specifies the address and R1 is read.
106
; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=B'0001000, A=1
;
MOV.L R0,@R1
; R1=H'F100 004C; data array access, entry=B'0000100, Way = 0, longword
; address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
Usage Examples
Invalidating Specific Entries
Reading the Data of a Specific Entry