HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 237

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bits 5 and 4—Area 6 Address OE/WE Assert Delay (A6TED1, A6TED0): These bits specify the
address to OE/WE assert delay time for the PCMCIA interface connected to area 6.
Bit 5: A6TED1
0
1
Bits 3 and 2—Area 5 OE/WE Negate Address Delay (A5TEH1, A5TEH0): These bits specify the
OE/WE negate address delay time for the PCMCIA interface connected to area 5.
Bit 3: A5TEH1
0
1
Bits 1 and 0—Area 6 OE/WE Negate Address Delay (A6TEH1, A6TEH0): These bits specify the
OE/WE negate address delay time for the PCMCIA interface connected to area 6.
Bit 1: A6TEH1
0
1
10.2.8
The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address
bus and is a virtual 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3.
SDMR settings must be made before synchronous DRAM is accessed.
Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If the
value to be set is X and the SDMR address is Y, the value X is written in the synchronous DRAM
mode register by writing in address X + Y. Since A0 of the synchronous DRAM is connected to
A2 of the chip and A1 of the synchronous DRAM is connected to A3 of the chip, the value
actually written to the synchronous DRAM is the X value shifted two bits right. For example,
when H'0230 is written to the SDMR register of area 2, random data is written to the address
Synchronous DRAM Mode Register (SDMR)
Bit 4: A6TED0
0
1
0
1
Bit 2: A5TEH0
0
1
0
1
Bit 0: A6TEH0
0
1
0
1
Description
0.5 cycle delay
1.5 cycle delay
2.5 cycle delay
3.5 cycle delay
Description
0.5 cycle delay
1.5 cycle delay
2.5 cycle delay
3.5 cycle delay
Description
0.5 cycle delay
1.5 cycle delay
2.5 cycle delay
3.5 cycle delay
(Initial value)
(Initial value)
(Initial value)
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