HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 173

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

8.7
The hardware standby mode is provided only in the SH7708S and SH7708R. This mode is not
supported in emulator.
8.7.1
Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode,
all modules except those operating on an RTC clock are halted, as in the standby mode entered on
execution of a SLEEP instruction.
Hardware standby mode differs from standby mode as follows.
1. Interrupts and manual resets are not accepted.
2. The TCLK clock output is fixed low.
3. The TMU does not operate.
4. In the SH7708S and SH7708R, the RTC continues to operate even if power is not supplied to
Operation when a low-level signal is input at the CA pin depends on the CPG state, as follows.
1. In standby mode
2. During WDT operation when standby mode is canceled by an interrupt
3. In sleep mode
4. During PLL standby (see section 9.6 for the PLL standby function)
Hold the CA pin low in hardware standby mode.
power supply pins other than those for RTC power. In this case, all output pins go to the non-
drive state. With the SH7708, it is not possible to supply power only to the RTC power
supply.
The clock remains stopped and the chip enters the hardware standby state. Acceptance of
interrupts and manual resets is disabled, TCLK output is fixed low, and the TMU halts.
The chip enters hardware standby mode after standby mode is canceled and the CPU resumes
operation.
The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes
operation.
The chip enters hardware standby mode after forced implementation of the PLL OFF state.
Hardware Standby Mode
Transition to Hardware Standby Mode
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