HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 16

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

10.2 BSC Registers.................................................................................................................... 200
10.3 BSC Operation................................................................................................................... 223
10.4 Usage Notes ....................................................................................................................... 297
Section 11 Timer (TMU)
11.1 Overview............................................................................................................................ 301
11.2 TMU Registers .................................................................................................................. 304
vi
10.1.4 Register Configuration ......................................................................................... 192
10.1.5 Area Overview...................................................................................................... 193
10.1.6 PCMCIA Support ................................................................................................. 196
10.2.1 Bus Control Register 1 (BCR1)............................................................................ 200
10.2.2 Bus Control Register 2 (BCR2)............................................................................ 203
10.2.3 Wait State Control Register 1 (WCR1)................................................................ 204
10.2.4 Wait State Control Register 2 (WCR2)................................................................ 206
10.2.5 Individual Memory Control Register (MCR)....................................................... 209
10.2.6 DRAM Control Register (DCR) .......................................................................... 214
10.2.7 PCMCIA Control Register (PCR)........................................................................ 216
10.2.8 Synchronous DRAM Mode Register (SDMR) .................................................... 217
10.2.9 Refresh Timer Control/Status Register (RTCSR) ................................................ 218
10.2.10 Refresh Timer Counter (RTCNT) ........................................................................ 220
10.2.11 Refresh Time Constant Register (RTCOR).......................................................... 221
10.2.12 Refresh Count Register (RFCR) .......................................................................... 221
10.2.13 Cautions on Accessing Refresh Control Related Registers.................................. 222
10.3.1 Endian/Access Size and Data Alignment ............................................................. 223
10.3.2 Description of Areas............................................................................................. 229
10.3.3 Basic Interface...................................................................................................... 232
10.3.4 DRAM Interface................................................................................................... 239
10.3.5 Synchronous DRAM Interface ............................................................................. 255
10.3.6 Pseudo-SRAM Direct Connection ....................................................................... 271
10.3.7 Burst ROM Interface ............................................................................................ 280
10.3.8 PCMCIA Interface................................................................................................ 283
10.3.9 Waits between Access Cycles .............................................................................. 295
10.3.10 Bus Arbitration ..................................................................................................... 296
10.4.1 Area 2 and 3 Bus Width Setting ........................................................................... 297
10.4.2 When Area 6 is Designated for PCMCIA, with a 16-Bit Bus Width................... 297
10.4.3 Self-Refreshing..................................................................................................... 298
10.4.4 PCMCIA Area Access.......................................................................................... 299
10.4.5 Note on DRAM Connection for Areas 2 and 3.................................................... 300
11.1.1 Features ................................................................................................................ 301
11.1.2 Block Diagram...................................................................................................... 301
11.1.3 Pin Configuration ................................................................................................. 303
11.1.4 Register Configuration ......................................................................................... 303
11.2.1 Timer Output Control Register (TOCR) .............................................................. 304
................................................................................................... 301