HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 88

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

3.4.4
When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of
virtual addresses are mapped onto a single physical address, the same physical address data will be
recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The
reason why this problem only occurs when using a 1-kbyte page is explained below with reference
to figure 3.10.
To achieve high-speed operation of the SH7708 Series cache, an index number is created using
virtual address bits 10–4. When a 4-kbyte page is used, virtual address bits 10–4 are included in
the offset, and since they are not subject to address translation, they are the same as physical
address bits 10–4. In cache-based address comparison and recording in the address array, since the
cache tag address is a physical address, physical address bits 31–10 are recorded.
When a 1-kbyte page is used, also, a cache index number is created using virtual address bits 10-4.
However, in the case of a 1-kbyte page, virtual address bit 10 is subject to address translation and
therefore may not be the same as physical address bit 10. Consequently, the physical address is
recorded in a different entry from that of the index number indicated by the physical address in the
cache address array.
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Virtual address 1 is recorded in cache entry H'00, and virtual address 2 in cache entry H'40. Since
the two virtual addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
virtual address. Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same
as a physical address already used in another TLB entry, it should be recorded in such a way that
physical address bit 10 is the same.
68
Virtual address 1 H'00000000
Virtual address 2 H'00000400
Avoiding Synonym Problems
physical address H'00000400
physical address H'00000400