HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 77

IC SUPERH MPU ROMLESS 144LQFP

HD6417708SF60

Manufacturer Part Number
HD6417708SF60
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708SF60

Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417708SF60
Manufacturer:
HITACHI
Quantity:
2 400
Part Number:
HD6417708SF60
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD6417708SF60
Manufacturer:
HIT
Quantity:
330
Part Number:
HD6417708SF60I
Manufacturer:
ACCMICRO
Quantity:
144
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Address Space Identifier (ASID): When multiple processes run in parallel sharing the same
virtual address space and the processes have unique address translation tables, the virtual space
can be multiplexed. The ASID is 8 bits in length and is held in PTEH within the MMU indicating
the current process. With ASID, the TLB need not be purged when the process is switched.
When multiple processes run in parallel using the virtual address space exclusively, the physical
address corresponding to a given virtual address is specified uniquely. For this kind of single
virtual memory, the ASID becomes a key to protect memory (see section 3.4.2).
3.1.4
A register that has an undefined initial value must be initialized by the software. Table 3.1 shows
the configuration of the MMU control registers.
Table 3.1
Name
Page table entry register
high
Page table entry register low
Translation table base
register
TLB exception address
register
MMU control register
Notes: 1. Initialized by a power-on reset or manual reset.
2. SV bit: undefined
Register Configuration
Other bits: 0
Register Configuration
Abbreviation
PTEH
PTEL
TTB
TEA
MMUCR
R/W
R/W
R/W
R/W
R/W
R/W
Size
Longword
Longword
Longword
Longword
Longword
Undefined
Undefined
Undefined
Undefined
*
Initial Value*
2
1
Address
H'FFFFFFF0
H'FFFFFFF4
H'FFFFFFF8
H'FFFFFFFC
H'FFFFFFE0
57

Related parts for HD6417708SF60