HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 23

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Table 1.1
Item
Memory
management
unit (MMU)
Cache memory
Interrupt
controller
(INTC)
User break
controller
(UBC)
SH7708 Series Features (cont)
Features
4 Gbytes of address space, 256 address spaces (8-bit ASID)
Supports single virtual memory mode and multiple virtual memory mode
Paging system
Supports multiple page sizes: 1 or 4 kbytes
128-entry, 4-way set associative TLB
Supports software selection of replacement method and random-replacement
algorithms
Contents of TLB are directly accessible by address mapping
Choice of operating mode
Mixed instruction/data, 128 entries, 16-byte block length
Selectable write method (write-back/write-through), LRU (least recently used)
replacement algorithm
Single-stage write-back buffer
Contents of TLB can be accessed directly by address mapping (can be used
as on-chip memory)
5 external interrupt pins (NMI, IRL0 to IRL3)
Encoded input of 15 external interrupt sources via pins IRL0 to IRL3
On-chip peripheral interrupts: priority levels set for each module
Supports debugging by user break interrupts
2 break channels
Addresses, data values, type of access, and data size can all be set as break
conditions
Supports a sequential break function
Normal mode (8-kbyte cache)
RAM mode (4-kbyte cache + 4-kbyte RAM)
4-way set associative (8-kbyte cache)
2-way set associative (4-kbyte cache)
3