HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 145

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

7.1.3
Table 7.1 shows the user break controller registers.
Table 7.1
Channel
A
B
Common
Notes: 1. Value is retained in standby mode.
7.1.4
The relationship between break conditions and register settings is as follows:
1. Break conditions for channel A or B are set in the respective registers.
2. The address is set in the BARA or BARB register. ASID is set in the BASRA or BASRB
3. Bus cycle break conditions are set in the BBRA or BBRB register. Settings are instruction
4. For channel B, data can be included in the break conditions. Data is set in the BDRB register.
register. Whether the address is included in the break conditions, or whether or not masking is
to be performed, is set in the BAMA or BAMB bit of the BAMRA or BAMRB register. If
ASID is included in the conditions, this is set in the BASMA or BASMB bit of the BAMRA or
BAMRB register.
fetch or data access, read or write, and data access size. In the case of an instruction fetch,
whether the break is to be made before or after instruction execution is set in the PCBA or
PCBB bit of the BRCR register.
If data is to be masked, it is set in the BDMRB register. Data inclusion in or exclusion from
break conditions is set in the DBEB bit of the BRCR register.
2. Initialized by power-on reset or manual reset.
Register Configuration
Break Conditions and Register Settings
UBC Registers
Register
BARA
BASRA
BAMRA
BBRA
BARB
BAMRB
BASRB
BBRB
BDRB
BDMRB
BRCR
Initial Value*
Undefined
Undefined
Undefined
H'0000*
Undefined
Undefined
Undefined
H'0000*
Undefined
Undefined
H'0000*
2
2
2
1
Access Size
Longword
Byte
Byte
Word
Longword
Byte
Byte
Word
Longword
Longword
Word
Access Address
H'FFFFFFB0
H'FFFFFFE4
H'FFFFFFB4
H'FFFFFFB8
H'FFFFFFA0
H'FFFFFFA4
H'FFFFFFE8
H'FFFFFFA8
H'FFFFFF90
H'FFFFFF94
H'FFFFFF98
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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