HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 154

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

7.3
7.3.1
The flow from break condition setting to user break trap processing is as follows:
1. In the break conditions, set the break address in the break address register for the relevant
2. Set the break bus conditions in the break bus cycle register (BBRA or BBRB). If 00 is set for
3. When a condition is matched, the condition match flag for the relevant channel (CMFA or
4. When sequential conditions are set, a break is made at the instruction matched by channel B
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channel (BARA or BARB), the ASID corresponding to the break space in the break ASID
register (BASRA or BASRB), and the address and ASID masking method in the break address
masking register (BAMRA or BAMRB). If the data bus value is included in the break
conditions, set the break data in the break data register (BDRB) and the data mask in the break
data mask register (BDMRB).
even one set out of BBRA/BBRB register instruction fetch/data access select and read/write
select, a user trap break will not be generated in the corresponding channel.
Set such specifications as pre- or post-execution in the case of instruction fetch, whether the
data bus value is to be included in the conditions in the case of data access, and independent or
sequential conditions for channels A and B, in the break control register (BRCR).
Set the BBRA and BBRB registers only after all other break-related register settings have been
completed. If break enabling is set with the BBRA and BBRB registers while the break
address, data, mask, and other registers are still in their initial post-reset state, a break may
occur inadvertently.
CMFB) is set. This flag is set by a condition match but is not reset. To confirm setting of the
same flag again, therefore, it should first be cleared to 0.
when the channel B condition is matched after matching of the channel A condition. No break
is made if the channel B set condition is matched before or at the same time as the channel A
condition.
With sequential conditions, the condition match flag is set only for channel B, and not for
channel A.
UBC Operation
User Break Operation Flow