HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 364

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

13.2
13.2.1
The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into
SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one
byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write
SCRSR directly.
13.2.2
The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of
one byte of serial data by moving the received data from the receive shift register (SCRSR) into
SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows
the SCI to receive data continuously.
The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby
or module standby mode.
13.2.3
The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the
transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit
data from SCTDR into SCTSR and starts transmitting again. If the TDRE bit in SCSSR is 1,
however, the SCI does not load the SCTDR contents into SCTSR. The CPU cannot read or write
to SCTSR directly.
344
Initial value:
Bit name:
Bit name:
Bit name:
Register Descriptions
Receive Shift Register (SCRSR)
Receive Data Register (SCRDR)
Transmit Shift Register (SCTSR)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
—
—
7
7
0
R
7
—
—
6
6
0
R
6
—
—
5
5
0
R
5
—
—
4
4
0
R
4
—
—
3
3
0
R
3
—
—
2
2
0
R
2
—
—
1
1
0
R
1
—
—
0
0
0
R
0